In a process for forming a multilayer interconnection structure of a semiconductor device, a plasma etching process for forming a recess such as a groove or a via hole of a damascene structure in an interlayer insulating film by using a photoresist film containing an organic material may be performed in order to form a conductive layer for connecting an upper and a lower wiring layer such as Cu via an interlayer insulating film formed of, e.g., SiOCH (compound containing silicon, oxygen, carbon and hydrogen) on a semiconductor wafer. Further, a SiCOH film having a dielectric constant lower than a SiO2 film is referred to as a low-k film.
A stopper film such as a SiCN (silicon carbonitride) film is formed between the interlayer insulating film and the lower wiring layer to thereby form a recess having a uniform depth within the interlayer insulating film of the wafer and reduce damages on the Cu surface. After the recess is formed in the interlayer insulating film, a plasma etching process such as brake is performed on the stopper film by using a processing gas containing, e.g., F (fluorine), as described in Patent Document 1, in order to expose an underlying Cu (wiring layer). Besides, a plasma processing may be performed using a processing gas containing O (oxygen). Thereafter, a cleaning process using, e.g., a liquid chemical, is performed and, then, a conductive layer is buried in the recess of the interlayer insulating film.
However, as described in Patent Document 2, a damaged layer having dangling bonds due to elimination of, e.g., C (carbon), is formed on a portion of the interlayer insulating film which contacts with the plasma by the plasma processing. When the wafer is transferred in a vacuum atmosphere or an atmospheric atmosphere, a small amount of moisture in the atmosphere adheres to the dangling bonds. Accordingly, an OH group or the like is coupled to Si, resulting in an increase of the dielectric constant of the interlayer insulating film. To solve this problem, there has been known a method including: forming a recess in an interlayer insulating film; supplying an organic gas containing, e.g., Si and C (carbon) to a wafer while heating the wafer in a chamber of a heat treating apparatus which is different from a chamber for performing a plasma processing; and performing a recovery process for substituting the OH group with, e.g., a methyl group.
However, Cu exposed by etching the stopper film may be mixed with, e.g., O or F in the processing gas used for the etching process. Further, deposits containing F and the aforementioned moisture may be deposited on the surface. Thus, if the conductive layer is buried in this recess, a part of the conductive layer is oxidized or fluorinated and becomes copper oxide or copper fluoride. Accordingly, the resistance of the conductive layer increases, and electrical characteristics of a semiconductor device deteriorate. When the wafer having the copper oxide or the copper fluoride is cleaned by a liquid chemical, the copper oxide or the copper fluoride is removed and, therefore, the wiring layer becomes thin. Further, HF (hydrogen fluoride) is generated by reaction between the copper fluoride or the deposits containing F and the moisture in the atmosphere or the liquid chemical. Hence, the Cu wirings are dissolved, and disconnected. If the recovery process is performed on the wafer to which the moisture adheres, a hydrophobic by-product such as silanol may be generated by reaction between the recovery process gas and the moisture. Since it is difficult to remove the silanol by the cleaning process, the electrical resistance of the semiconductor device is increased. Hence, in order to obtain a semiconductor device containing small damages in an interlayer insulating film and a small amount of oxide in a wiring layer, a complicated process is required and this may decrease a throughput. Patent Documents 3 and 4 describe therein a technique for performing a reduction process on the wiring layer. However, the above-described problems are not described in Patent documents 3 and 4.    Patent Document 1: Japanese Patent Laid-open Publication No. 2007-250861    Patent Document 2: Japanese Patent Laid-open Publication No. 2007-80850 (paragraph [0008])    Patent Document 3: Japanese Patent Laid-open Publication No. 2006-019601    Patent Document 4: Japanese Patent Laid-open Publication No. 2009-164471